Key Metrics Topology: 5×5 Mesh / Torus NoC Routing Algorithms: XY_CLASSIC, BALANCE_DOR, ADAPTIVE_XY Duration: 4 Months Verification Methodology: UVM / SystemVerilog Coverage Closure: 98.7% Regression: 426 Runs Project Overview A Network-on-Chip (NoC) serves as the communication backbone of modern System-on-Chip (SoC) designs, enabling high-bandwidth, low-latency
Key Metrics Processor Core: ARM Cortex-M23 Power States Validated: 5 Duration: 10 months Verification Methods: 2 (UVM + C-based debug driver) Debug Interface: JTAG / SWD Application: Automotive TPMS Engagement Period: March 2024 –
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We aim to provide value added services to Indian, European and American Semiconductor Product and Services Companies.
