Functional Verification of TPMS SoC with ARM Cortex-M23

Key Metrics

• Processor Core: ARM Cortex-M23
• Power States Validated: 5
• Duration: 10 months
• Verification Methods: 2 (UVM + C-based debug driver)
• Debug Interface: JTAG / SWD
• Application: Automotive TPMS
• Engagement Period: March 2024 – January 2025
• Safety Context: ISO 26262 awareness

Project Overview

Keenheads partnered with a semiconductor company’s automotive SoC division to deliver functional verification of a low-power Tire Pressure Monitoring System (TPMS) SoC built on an ARM Cortex-M23 core. This project aimed to deliver full functional sign-off ahead of tapeout, covering processor boot and execution, power management, and interrupt-driven sensor behavior — combining pre-silicon UVM simulation with a post-silicon C-based debug driver so each method covered ground the other could not.

Key Project Components

1. UVM-Based Pre-Silicon Verification
   • Keenheads built a UVM environment providing block- and subsystem-level coverage of the System Controller, NVIC, Wakeup Controller FSM, and memory-mapped register logic.
   • Constrained-random and directed sequences, functional coverage, and protocol assertions closed the state space ahead of tapeout, catching defects that would otherwise surface only after silicon existed.
2. C-Based Test Execution via Debug Driver
   • Once UVM signed off the RTL, the same execution paths — instruction fetch, register file operations, exception handling, and TrustZone secure/non-secure transitions — were re-validated on actual silicon.
   • Directed C test cases run through the JTAG/SWD debug interface confirmed that RTL behavior translated correctly into real hardware.
3. System Controller Verification
   • Clock gating sequences, reset domain behavior, and power domain control register programming were checked in simulation, then re-confirmed on silicon.
   • This dual-track approach ensured the System Controller did not leave the SoC in an unstable state after real power-on events that simulation could not fully model.
4. Wakeup Controller and Power State FSM Validation
   • All five Wakeup Controller power-state transitions — including wake-on-interrupt from simulated pressure sensor events, threshold-crossing conditions, and RF signal assertions — were verified across both UVM and silicon.
   • This ensured the low-power TPMS SoC would reliably wake on the correct trigger in the field, not just in test.
5. Interrupt Priority and Latency Validation
   • NVIC priority arbitration, ISR entry/exit timing, and nested interrupt sequences were exercised in both the UVM environment and the post-silicon debug driver.
   • Deterministic interrupt response was validated as critical to automotive TPMS reliability, where a delayed alert can mean a missed warning.
6. Debug-Driven Memory and Register Inspection
   • JTAG-based hardware breakpoints and memory inspection made execution flow and register state visible in ways simulation alone could not.
   • This caught register initialization bugs and confirmed on-chip SRAM read/write integrity before they could surface downstream.
7. Multi-Method Correlation of UVM and Silicon Results
   • Findings from pre-silicon UVM simulation were re-validated once the Cortex-M23 debug architecture was available on silicon, using a second, JTAG-based test layer.
   • This closed the gap between simulation and real hardware, confirming timing and integration behavior that simulation alone could not guarantee — and avoiding a costly post-tapeout re-spin.