Key Metrics
Topology: 5×5 Mesh / Torus NoC
Routing Algorithms: XY_CLASSIC, BALANCE_DOR, ADAPTIVE_XY
Duration: 4 Months
Verification Methodology: UVM / SystemVerilog
Coverage Closure: 98.7%
Regression: 426 Runs
Project Overview
A Network-on-Chip (NoC) serves as the communication backbone of modern System-on-Chip (SoC) designs, enabling high-bandwidth, low-latency communication between processor cores, memories, and peripherals. KeenHeads developed a reusable UVM Verification IP (VIP) for a parameterized Network-on-Chip (NoC) fabric to accelerate SoC verification before tapeout.
The reusable NoC verification environment supported both Mesh and Torus topologies while validating multiple routing algorithms using constrained-random verification, cycle-accurate scoreboard, functional coverage, and self-checking mechanisms. The VIP was designed for scalability, allowing topology, routing algorithm, and grid-size changes without requiring modifications to the UVM testbench.
Verification Challenges
The engagement focused on four key challenges:
- Detecting routing deadlocks under heavy concurrent traffic.
- Supporting both Mesh and Torus topologies using a common reusable UVM environment.
- Building a cycle-accurate reference model for routing validation.
- Verifying adaptive and deterministic routing algorithms.
- Achieving functional coverage across hundreds of source-to-destination routing combinations.
- Validating packet flow under congestion, backpressure, and credit starvation.
UVM Verification Solution
A reusable layered UVM Verification IP was developed using configurable agents, drivers, monitors, scoreboards, and functional coverage components. Configuration was centralized through reusable configuration objects, enabling the same verification environment to support multiple NoC architectures without testbench changes.
The NoC verification environment included:
- Cycle-accurate routing reference model
- Constrained-random packet generation
- Functional coverage model
- Protocol assertions
- Self-checking scoreboard
- Negative testing scenarios
- Reusable UVM sequence library
- Automated regression framework
The verification infrastructure enabled rapid validation of different NoC configurations while significantly reducing the verification effort for future SoC programs.
Verification Scenarios
Major Network-on-Chip verification scenarios included:
- Packet routing verification across all routers
- Source-to-destination routing validation
- Mesh and Torus topology verification
- Adaptive and deterministic routing verification
- Simultaneous multi-router traffic stress testing
- Localized sub-network traffic validation
- Congestion and hotspot traffic scenarios
- Backpressure and credit-starvation verification
- Negative protocol testing
- Error injection and recovery testing
Issues Found
The verification campaign identified and resolved three critical issues before design sign-off:
- Virtual channel credit-return race under sustained traffic
- Torus boundary routing calculation error
- VIP illegal-address checker defect
All issues were successfully reproduced, debugged, fixed, and verified through complete regression, ensuring robust NoC functionality before integration.
Coverage & Sign-off
The project achieved:
- 98.7% functional coverage
- 100% scoreboard self-check coverage
- Zero open High-severity issues
- 426/426 regression runs passing
- Verification sign-off completed for SoC integration
