Key Metrics Processor Core: CV32E40P (RI5CY) Debug Interfaces: JTAG • DMI • SBA Duration: 5 Months Coverage Closure: 97% Functional / 94% Line Regression Platforms: VCS • QuestaSim • Verilator Issues Closed: 14 Project
Key Metrics Topology: 5×5 Mesh / Torus NoC Routing Algorithms: XY_CLASSIC, BALANCE_DOR, ADAPTIVE_XY Duration: 4 Months Verification Methodology: UVM / SystemVerilog Coverage Closure: 98.7% Regression: 426 Runs Project Overview A Network-on-Chip (NoC) serves as the communication backbone of modern System-on-Chip (SoC) designs, enabling high-bandwidth, low-latency
Key Metrics Processor Core: ARM Cortex-M23 Power States Validated: 5 Duration: 10 months Verification Methods: 2 (UVM + C-based debug driver) Debug Interface: JTAG / SWD Application: Automotive TPMS Engagement Period: March 2024 –
Key Metrics Technology 28HPC+ TSMC Die Size 10+ sqmm Gate Count 15 Million Frequency 5.4Ghz to 500Mhz Hier Blocks 6 Package WLSP BGA Duration 6- months Team Size 10 Project Overview Keenheads partnered
Key Metrics Technology 16ffc TSMC Die Size 16 sqmm Gate Count 30 Million Frequency 500Mhz Hier Blocks 6 Package Flip Chip BGA Duration 12 months Team Size 14 Project Overview Keenheads collaborated with
Key Metrics Technology 16ffc TSMC Die Size 65 sqmm Gate Count 100 Million Frequency 450Mhz Hier Blocks 13 Package Flip Chip BGA Duration 9 months Team Size 25 Project Overview Keenheads partnered with a
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