Key Metrics
Processor Core: CV32E40P (RI5CY)
Debug Interfaces: JTAG • DMI • SBA
Duration: 5 Months
Coverage Closure: 97% Functional / 94% Line
Regression Platforms: VCS • QuestaSim • Verilator
Issues Closed: 14
Project Overview
RISC-V Debug Module Verification was performed for a debug module compliant with the RISC-V Debug Specification v0.13, integrated with a CV32E40P (RI5CY) processor and a proprietary accelerator extension.
The engagement focused on validating debug functionality across processor halt and resume, JTAG and Debug Module Interface (DMI) transactions, firmware loading through System Bus Access (SBA), register and CSR programming, interrupt handling, and debug interaction with the custom accelerator pipeline.
Rather than relying on external debug tools such as OpenOCD or SimJTAG, a class-based JTAG driver was developed to autonomously execute full debug-session sequences, including TAP reset, IDCODE validation, DMI access, SBA firmware loading, abstract command execution, and processor resume operations.
SystemVerilog Assertions (SVA) independently monitored protocol behavior, providing an additional layer of checking for debug interface compliance and error conditions.
Verification Challenges
The engagement involved several verification challenges associated with both standard RISC-V debug functionality and interaction with the proprietary processor extension:
- Validating debug operations across standard processor functionality and custom accelerator execution paths
- Ensuring protocol compliance with the RISC-V Debug Specification v0.13
- Verifying firmware bring-up through the debug module using System Bus Access
- Handling processor halt and resume during multi-cycle accelerator transactions
- Validating register and CSR access through debug operations
- Verifying interrupt behavior during debug state transitions
- Testing malformed DMI transactions and SBA error conditions
- Maintaining consistent verification behavior across multiple simulators
RISC-V Debug Module Verification Solution
A reusable class-based verification environment was developed to execute and validate debug operations across the processor and its custom accelerator extension.
The verification environment included:
- Autonomous JTAG/DMI driver
- TAP reset and IDCODE validation
- DMI transaction generation and checking
- System Bus Access for firmware loading and memory transactions
- Abstract command execution
- Register and CSR programming and readback validation
- Assertion-based protocol checking using SystemVerilog Assertions
- Self-checking debug verification framework
- Directed sequences for error injection and corner-case testing
- Simulator-independent verification flow
- Cross-platform regression support using VCS, QuestaSim, and Verilator
The environment independently checked debug and protocol behavior while executing debug sequences without requiring external debug software.
Verification Scenarios
Major verification scenarios included:
- JTAG TAP reset and state transition verification
- IDCODE validation
- JTAG instruction and data register access
- DMI request and response validation
- Debug module register access
- Processor halt and resume verification
- SBA firmware loading and memory access
- Abstract command execution
- General-purpose register access
- CSR programming and readback validation
- Interrupt handling during debug operations
- Custom accelerator interaction during processor halt and resume
- Multi-cycle accelerator transaction handling
- Protocol error injection
- Malformed DMI transaction testing
- SBA busy and error-condition testing
- Negative protocol testing
Issues Found
Verification identified and resolved 14 issues before sign-off. Representative issues included:
SBA Transaction Handling
Issue: SBA requests were accepted while a previous SBA transaction was still busy, resulting in incorrect transaction handling and violating the expected debug protocol behavior.
Resolution: The issue was reproduced using directed verification sequences, corrected in RTL, and verified through targeted regression.
Accelerator Halt and Resume Interaction
Issue: Halt requests issued during multi-cycle accelerator transactions could leave stale bus grants after processor resume.
Resolution: The issue was reproduced through targeted halt and resume scenarios, corrected in RTL, and verified through regression.
DMI and SBA Error Handling
Issue: Malformed DMI transactions and injected SBA error conditions exposed protocol-handling issues.
Resolution: The identified behavior was reproduced using negative testing and error injection, corrected in RTL, and validated through targeted verification and regression.
Each issue was tracked through reproduction, RTL correction, and verification before closure.
Coverage & Sign-off
The project achieved:
- 97% Functional Coverage
- 94% Line Coverage
- 92% Branch Coverage
- Cross-simulator regression using VCS, QuestaSim, and Verilator
- 14 Issues Closed
- Zero Open High-Severity Issues
- Coverage Waivers Reviewed and Approved
- Successful Client Sign-off
The reusable verification environment enabled consistent validation of RISC-V debug functionality across multiple simulators while covering processor-specific accelerator interactions and debug protocol behavior before final sign-off.
