Wireline VDSL+ Modem System On Chip

Key Metrics

• Technology 16ffc TSMC
• Die Size 16 sqmm
• Gate Count 30 Million
• Frequency 500Mhz
• Hier Blocks 6
• Package Flip Chip BGA
• Duration 12 months
• Team Size 14

Project Overview

Keenheads collaborated with a leading technology firm to develop a high-performance Wireline VDSL+ Modem System on Chip (SoC). This project aimed to provide a robust and efficient solution for enhanced digital subscriber line (VDSL) communications, catering to the increasing demand for high-speed internet connectivity.

Key Project Components

1. SoC Synthesis, Constraints Generation, and LEC
   • Keenheads undertook the SoC synthesis process to ensure the logical design adhered to specified requirements.
   • Detailed constraints generation was carried out to optimize the SoC’s performance and efficiency.
   • Logic Equivalence Checking (LEC) was performed to validate the synthesized design against the original specifications, ensuring accuracy and consistency.
2. SoC Partitioning and Floorplan
   • The SoC was strategically partitioned to facilitate a streamlined design process and efficient resource utilization.
   • An optimal floorplan was created to maximize performance and integration of the SoC components.
3. SoC Place and Route (PnR) and Physical Verification
   • The place and route process was meticulously executed to position components accurately and establish efficient routing paths.
   • Rigorous physical verification was conducted to ensure the design conformed to all design rules and constraints, maintaining high standards of quality and reliability.
4. SoC Static Timing Analysis
   • Static Timing Analysis (STA) was performed to evaluate and optimize the timing performance of the SoC, ensuring it met the stringent requirements for VDSL applications.
5. IO Ring Design and ESD Reliability Verification
   • A robust IO ring design was implemented to manage inputs and outputs effectively.
   • Electrostatic Discharge (ESD) reliability verification was conducted using the client’s proprietary tool, ensuring the design’s resilience and durability against ESD events.
6. DFT STA Constraints Development and Timing Closure
   • Design for Test (DFT) STA constraints were developed to facilitate comprehensive testing and validation of the SoC.
   • Timing closure was achieved through detailed analysis and optimization, ensuring the SoC met all timing constraints and delivered reliable performance.
7. Project Schedule Planning and Management
   • Keenheads implemented a meticulous project schedule, managing the design and integration of all blocks and the top-level SoC.
   • Effective project management strategies were employed to mitigate risks and address challenges, ensuring timely project completion and delivery.

Conclusion

Keenheads successfully developed a high-performance Wireline VDSL+ Modem SoC by leveraging advanced design techniques, thorough planning, and collaborative efforts. This project exemplifies Keenheads’ commitment to delivering innovative and reliable solutions, setting new standards in the telecommunications industry