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Design Engineer - DFT

Role : Manage 2 -3 hierarchical blocks, DFT simulations, debug , pattern generation. Support scan chain insertion and post silicon debug

Desired Skills:

DFT logic integration and verification using testmax / tessent / modus
Experience on improving coverage.
Gate Level DFT verification with and without timing using vcs / ncsim.
Pattern generation, verification and delivery to ATE team.
Post silicon debug and support on failing patterns.
Good experience on EDA tools of reputed vendor like Mentor, Synopsis.
LBIST experience is a plus.
DFT mode STA and timing closure support is a plus

Experience : 2 to 3 Years

Design Engineer - DFT

Role : Manage 2 -3 hierarchical blocks, DFT simulations, debug , pattern generation. Support scan chain insertion and post silicon debug

Desired Skills:

DFT logic integration and verification using testmax / tessent / modus
Experience on improving coverage.
Gate Level DFT verification with and without timing using vcs / ncsim.
Pattern generation, verification and delivery to ATE team.
Post silicon debug and support on failing patterns.
Good experience on EDA tools of reputed vendor like Mentor, Synopsis.
LBIST experience is a plus.
DFT mode STA and timing closure support is a plus

Experience : 2 to 3 Years

Sr. Design Engineer - DFT

Role : Manage hierarchical blocks and pattern retargetting to top level, simulations debug and can think of different ways to improve coverage, scan insertion and post silicon bringup.

Desired Skills:

Good experience in scan insertion and ATPG in block level and pattern retargetting in top level.
DFT logic integration and verification using testmax / tessent / modus
Experience on improving coverage and can support with innovative ways to improve coverage.
Gate Level DFT verification with and without timing using vcs / ncsim.
Pattern generation, verification and delivery to ATE team.
Post silicon debug and support on failing patterns.
Good experience on EDA tools of reputed vendor like Mentor, Synopsis.
JTAG and MBIST/LBIST insertion and pattern generation.
Can manage and resolves scan issues, DRCs for small teams.

Experience : 4 to 6 Years

Technical Lead Engineer - DFT

Role : Derive DFT architecture for a SOC in collaboration with product engineering team. Plan and track DFT implementation. Guide other DFT members in implementing DFT for hierarchical SOC. Support post silicon debug

Desired Skills

5+ tapeout as DFT lead/Sr DFT engineer.
DFT architecture definition w.r.t. test time/cost, coverage, test power. Good experience/concept on all aspect of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan.
DFT logic integration and verification.
Experience on debugging low coverage.
Gate Level DFT verification with and without timing.
Pattern generation, verification and delivery to ATE team.
Post silicon debug and support on failing patterns.
Experience of leading small DFT team is plus.
Good experience on EDA tools of reputed vendor like Mentor, Synopsis. LBIST experience is plus.
DFT mode STA and timing closure support.

Experience : 6 to 9 Years

Design Engineer - Synthesis and STA

Role : Perform Synthesis for SOC and Blocks. Understand and develop synthesis/STA constraints.Perform timing Sign-Off and generate timing ECOs.

Desired Skills

Good understanding of Synthesis/STA concepts (Synthesis, Timing, Equivalence Checks, Extraction, Noise, Power, UPF/CPF)
Perform synthesis based on Power/Performance/Area/Schedule targets.
Timing Constraints generation for synthesis and Timing signoff.
Logical Equivalence between RTL to Netlist and Netlist to Netlist.
Netlist handoff lint checks.
Understanding of Timing closure with Analog PHYs and external interfaces like RGMII, GMII, SDHC, SPI etc. is a plus.
Hands-on experience with Design compiler/RTL compiler/ Genus and primetime/tempus.
Good scripting skills (TCL/Perl)
Familiarity with PD concepts/flow and assist PD team if and when required

Experience : 2 to 3 Years

Design Engineer – Physical Design

Role : Take up ownership of blocks independently (RTL2GDSII)

Desired Skills:

Interaction with RTL designers on timing paths.
Functional and DFT constraint development exposure.
Based on PPA targets, should be able to implement different floorplans.
Come up with strategies to control congestion through understanding of specific block level challenges.
Should be able to built the clock tree on multi-clocks, synchronous and asynchronous clock domain partitions.
Should be good in timing analysis.
Ability to own DRC/LVS/ANTENNA clean ups at block level.
Implementation experience on IR/EM analysis and fixes.
Should be good in innovus/icc2, tempus/primetime & genus/design compiler
Have low power implementation experience & should be good in scripting.

Experience : 2 to 3 Years

Design Engineer – Physical Verification & Reliability

Role : Take up ownership of physical verification and Reliability of blocks and fullchip

Desired Skills:

Interaction with Physical designers on DRC, LVS, manufacturing and reliability targets.
PV and IR/EM flow development exposure.
Understanding DRM and EM rules of target technology.
Come up with strategies for faster physical verification and reliability closure.
Should be able to understand the power intent of design and analog integration guidelines.
Should be good in debug and analysis.
Ability to own milestone and schedule tracking for DRC/LVS/ANTENNA clean ups at block level and fullchip level.
Implementation experience on IR/EM analysis and fixes.
Should be having working knowledge in innovus/icc2 and klayout/virtuoso
Have low power implementation experience & should be good in scripting.

Experience : 2 to 3 Years

Sr. Design Engineer – Physical Design

Role : Manage 2 block level Physical Design and Timing Closure. Guide other team members on PnR challenges

Desired Skills

Ability to manage multiple floorplan, place and Route of blocks using icc2 / innovus
Ability to converge timing using primetime / tempus
Ability to converge physical verification and IR & EM using calibre / pvs / icv and redhawk / voltus
Managing & Reporting Schedule and Status of deliverables
Clarity in Communication
Updating and understanding of Timing Constraints.
Scripting and Automation skills

Experience : 3-5 Years

Design Engineer-RTL

Desired Skills:

Hands-on experience with focus on front-end complex RTL design involving logic IP design.
Efficient in Coding in Verilog
Creating testbenches in Verilog or UVM
Running simulations using ncsim, vcs or similar tools
Debugging design issues using waveform viewers
Creating SDC and UPF constraints for synthesis.
Understanding timing reports.
Must be familiar with all stages of the ASIC design flow (including specification, architecture, and design implementation)
Highly motivated and skillful at solving difficult technical problems
Experience with scripting in Perl/Python/Shell

Experience : 2 to 4 Years

Sr Design Engineer-RTL

Role :

Perform detailed block design from system requirements and evolving specifications. Perform RTL coding, Lint checks, CDC tests, creating timing constraint file. Working closely with Synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power, and area goals

Desired Skills:

Creating Design Methodology, Micro-architecture, RTL coding in Verilog
Domain knowledge of high speed IP (USB, PCIe, DDR) or Processors (RISC-V or ARM)
Efficient in Coding in Verilog
Creating testbenches in Verilog or UVM
Running simulations using ncsim, vcs or similar tools
Debugging design issues using waveform viewers
Creating SDC and UPF constraints for synthesis.
Understanding timing reports.
Equivalence checking using formality or conformal.

Experience : 4 to 6 Years

Technical Lead Engineer-RTL

Role :

The RTL Lead Engineer performs detailed block design from system requirements and evolving specifications. Perform RTL coding, Lint checks, CDC tests, creating timing constraint file. Working closely with Synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power, and area goals

Desired Skills:

Develop HW architecture from specification documents.
Owning responsibilities include writing RTL code for IP development/RTL integration, checking the code for Lint/CDC issues, checking synthesizability and timing quality of the design, checking low power implementation, supporting verification team with debug and support physical design teams on timing constraints and other design topics using Verilog/System Verilog/VHDL.
Develop and execute low power design intent (UPF/CPF).
Design top level RTL, integration of blocks, clocks, resets, configuration registers, etc
Knowledge of low-speed bus protocols (AMBA/OCP) and high-speed serial protocols (PCIe/USB/Ethernet) will used at various stages of the design.
Awareness of DFT concepts to be used to fix functional violation that may get introduced which including DFT structures.
Carry out static checks including Lint/CDC (Spyglass), synthesis, LEC and STA. Debugging and fixing functional break.
Take ownership of tasks and drive tasks to closure
Must have gone through at least 3 tape-out of a large, high speed designs

Experience : 6 to 9 Years

Design Engineer - Verification

Role : Perform verification using UVM and SVM on IP, Blocks and top.

Desired Skills:

Ability to understand RTL quickly
familiar with ASIC/FPGA verification methodology
able to create a Verilog/VHDL module test specification from the ASIC/FPGA functional specification
should have the Knowledge of the System Verilog’s Universal Verification Methodology (UVM)

Experience : 2 to 3 Years

Sr. Design Engineer - Verification

Role : Perform verification using UVM and SVM on multiple IP, Blocks and top.

Desired Skills:

Experience working of SV and UVM methodology and knowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB, AXI, RISC-V, AMBA, DDR or similar is required, must have executed at-least 1 IP or SoC Verification projects.
Experience in setting up and debugging functional and/or gate-level simulations
Experience in translating functional requirements into verification plans
Experience in developing verification environment and regression setup.
Coverage analysis and closure.
Familiarity with using 3rd party VIPs
Good handle on Scripting (Python/Perl/shell).

Experience : 4 to 6 Years

Technical Lead Engineer - Verification

Role : Verification of the design, architecture and micro-architecture at pre-silicon, emulation, and post-silicon activities

Desired Skills:

Experience working of SV and UVM methodology and knowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB, AXI, RISC-V, AMBA, DDR or similar is required, must have executed at-least 3 IP or SoC Verification projects
Experience in setting up and debugging functional and/or gate-level simulations
Experience in translating functional requirements into verification plans
Experience in developing verification environment and regression setup.
Evaluating and using 3rd party VIPs
Coverage analysis and closure.

Experience : 6 to 9 Years

Design Engineer - FPGA

Desired Skills:

Experience in design, development, and verification of complex FPGAs.
RTL development in VHDL/Verilog/system Verilog
Familiar with Xilinx/ Altera FPGAs.
Familiar with Xilinx ISE, Vivado/ Altera Quartus FPGA tools
Experience in Functional verification using modelSim

Experience : 3 to 5 Years

Business Development – Manager

Role :

Support the commercial aspects of semiconductor design projects.
Market Research of semiconductor services and custom silicon development trends
Closely work with Management to define, guide and pursue revenue and profits growth trajectory.
Build and manage a portfolio of customers in need of ASIC design services.
Advise and promote the most optimal design approaches for end application of customer’s products.
Prepare quotations, negotiate & finalize contracts and agreements terms.
Track and report on sales activities and performance metrics
Provide forecasts for and updates of the business.

Desired Skills:

Strong Knowledge of the digital ASIC design flows and parameters influencing the efforts of the tasks.
Dealt with world leading IP vendors, EDA vendors and chip foundries for ASIC design.
Excellent verbal and written communication in English (Knowledge of Japanese, Taiwanese or Korean is a big advantage)
Experience in a customer-facing role preferred.
Very strong in using Excel and PowerPoint.

Requirements :

8 to 12 Years (of which 5 years in Business Development)
Bachelors or Masters Degree

Bangalore preferred (can be remote also)

Internships

Software Intern – ML Business Applications

Qualifications

Pursuing a Bachelor’s or Master’s degree in Computer Science, Information Systems, Data Science or similar

Eligible for CPT or OPT during the term.

Experience with Python’s scientific libraries (numpy, scipy, matplotlib, etc.)
Experience with training and verifying machine learning and deep learning models in frameworks such as TensorFlow or PyTorch
Good verbal and written communication skills

Benefits

Each intern will receive a competitive stipends.

Responsibilities

You will contribute to operations group with AI-assisted enhancements to our applications
Research, build, train, and quantitatively/qualitatively assess deep learning models
Identify and capture datasets from different sources for model development, which may include discovering, recording, simulating, cleaning, and pre-processing the data
Provide demonstrations of the concept, design, and results
Document all design, experiments, and results

Apply before 30-Aug-2024

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Careers

Openings

Design Engineer - DFT

Design Engineer - DFT

Sr. Design Engineer - DFT

Technical Lead Engineer - DFT

Design Engineer - Synthesis and STA

Design Engineer – Physical Design

Design Engineer – Physical Verification & Reliability

Sr. Design Engineer – Physical Design

Design Engineer-RTL

Sr Design Engineer-RTL

Technical Lead Engineer-RTL

Design Engineer - Verification

Sr. Design Engineer - Verification

Technical Lead Engineer - Verification

Design Engineer - FPGA

Business Development – Manager

Internships

Software Intern – ML Business Applications

ASIC Design Consulting Company

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