We are Hiring


Come and join wonderful ASIC design community at KeenHeads.

Explore and learn all aspects of ASIC design. Get to know what it takes to build a System-On-Chip ASIC .


We value potential over experience.

At keenheads we strive to ensure that each assignment or project has a value for individuals working on it. We focus on all round development of individuals.

Job Openings

Send Your resume to geeta@keenheads.com

Job Description
  • Manage a full Physical Design Project and Track schedule.
  • Work with multisite teams for RTL to GDSII implementation
  • Top level Floorplanning and Place & Route
  • Lead Auto PnR of physical design partitions
  • Physical Verification of partitions
  • Reliability Analysis (SI/IR/PDN)
  • Drive PnR methodology and automation of reports generation.
Key Skills Required
  • Ability to manage Physical Design Project
  • Ability to Floorplan and Partition a design
  • Managing & Reporting Schedule and Status of Project
  • Well Versed with Auto place and route, Timing closure and Physical verification
  • Clarity in Communication
  • Timing Constraints know-how
  • Scripting and Automation skills
Experience : 8-11 Yrs

(have low experience but high potential, you are welcome !!)

Location : Noida
Job Description
  • Understanding SOC or Block design architecture.
  • Creating verification plan.
  • Tracking schedule.
  • Guiding verification members for creating testcases, simulations, debug and methodology.
  • Technical guidance and mentoring team
Key Skills Required
  • Plan, develop, debug Testbench and Verification Suite at IP module and SoC level.
  • Good experience in SoC level testing with booting checks, connectivity checks
  • Aware of protocols and NOC testing is added advantage
  • Assertion based verification or working experience on formal verification (IFV, Jasper)
  • Good knowledge of SV, UVM, VVM etc
  • Added advantage if CPU based testing like ARM CPU based testing with booting
  • Exposure to GLS verification with and without SDF
  • Technical troubleshooting, debugging and demonstrated problem solving skills
  • Experience on any of the defect management tools
Experience : 8+ Years. Must have led 2 SOC or Multiple Block verification
Location : Noida
Job Description
  • Manage 1-2 block level Physical Design and Timing Closure.
  • Guide other team members on PnR challenges
Key Skills Required
  • Ability to manage multiple Physical Design Partitions
  • Ability to Floorplan and Partition a design
  • Managing & Reporting Schedule and Status of Project
  • Well Versed with Auto place and route and timing closure
  • Clarity in Communication
  • Timing Constraints know-how
  • Scripting and Automation skills
Experience : 3-8 Yrs

(have low experience but high potential, you are welcome !!)

Location : Noida
Job Description
  • Place and Route for partition.
  • Automation of manual tasks
Key Skills Required
  • Place and Route tool know-how
  • Ability to Floorplan a design
  • Block Level Physical Verification
  • Clarity in Communication
  • Scripting and Automation skills
Experience : 1-3 Yrs
Location : Noida
Job Description
  • Manage 2 -3 hierarchical blocks
  • DFT simulations and debug
  • Scan pattern generation.
  • Support scan chain insertion and post silicon debug
Key Skills Required
  • DFT logic integration and verification.
  • Experience on improving coverage.
  • Gate Level DFT verification with and without timing.
  • Pattern generation, verification and delivery to ATE team.
  • Post silicon debug and support on failing patterns.
  • Good experience on EDA tools of reputed vendor like Mentor, Synopsis. LBIST experience is plus.
  • DFT mode STA and timing closure support.
Experience : 2-5 Yrs
Location : Noida
Job Description
  • Design Verification of digital blocks, IP or SoC Verification (specs. understanding and micro-architecture definition)
Key Skills Required
  • Strong SV, UVM VVM skills
  • Good knowledge in any of the protocols like Ethernet/PCIE/USB/DDR/AXI/SATA/MIPI etc
  • Experienced in developing test bench components, writing tests and coverage tuning
  • Digital Design and Verification Verilog/System-verilog
Experience : 2-5 Yrs
Location : Noida